Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 10/21/2021
Document Table of Contents

1.2.6. Interface Signals

Table 6.  Interface Signals for 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
Signal Direction Description
pll_refclk0 Input

Reference clock for the E-tile Native PHY transceiver. Set this clock to 156.25 MHz.

iopll_refclk Input Reference clock for IOPLL. Set this clock to 100 MHz. The output frequencies are 125 MHz and 62.5 MHz. The clocks driven out are tx_clk_125,rx_clk_125, tx_clk_62_5, and rx_clk_62_5.
reg_clk Input Clock for configuring CSR registers. Set this clock to a frequency less than or equal to 125 MHz.
tx_serial_data Output Positive signal for the transmitter serial data.
tx_serial_data_n Output Negative signal for the transmitter serial data.
rx_serial_data Input Positive signal for the receiver serial data.
rx_serial_data_n Input Negative signal for the receiver serial data.
channel_ready_n Output When deasserted, this signal indicates that the Native PHY RX and TX datapath resets sequencing are completed and the rx_is_lockedtodata signal of Native PHY is asserted.

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