Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 10/21/2021
Document Table of Contents Design Components

Table 5.  Design Components
Component Description
Triple-Speed Ethernet Intel® FPGA IP

The Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) is instantiated with the following configuration:

  • Core Configurations:
    • Core Variation: 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS
    • Use internal FIFO: Not selected
    • Transceiver type: None
  • MAC Options:
    • Enable magic packet detection: Selected
    • Align packet headers to 32-bit boundary Not selected
    • Include statistics counters: Selected
  • Timestamp Options:
    • Enable timestamping: Not selected
  • PCS/Transceiver Options:
    • Enable SGMII bridge: Selected
External E-tile Transceiver PHY External E-tile transceiver Native PHY with 2XTBI interface.
Client Logic Generates and monitors packets sent or received through the IP.
Ethernet Traffic Controller Controlled via Avalon® memory-mapped interface.
JTAG to Avalon® memory-mapped interface Address Decoder Convert JTAG Signals for Avalon® memory-mapped interface.

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