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1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
3. Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
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1.2.1. Features
- Generates the design example for Triple-Speed Ethernet MAC without internal FIFO and 2XTBI PCS IP variant with external E-tile transceiver.
- Generates traffic at the transmit path and loops back to the receive path through external E-tile transceiver PHY.
- TX and RX serial loopback mode through external PHY.
- Supports packet statistics report on both MAC transmitter and MAC receiver.
- Supports System Console user interface. You can make use of the TCL-based user interface to dynamically configure and monitor any registers in this design example.
- Basic packet checking capabilities of traffic monitor.
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