Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 10/21/2021
Document Table of Contents

1.2.1. Features

  • Generates the design example for Triple-Speed Ethernet MAC without internal FIFO and 2XTBI PCS IP variant with external E-tile transceiver.
  • Generates traffic at the transmit path and loops back to the receive path through external E-tile transceiver PHY.
  • TX and RX serial loopback mode through external PHY.
  • Supports packet statistics report on both MAC transmitter and MAC receiver.
  • Supports System Console user interface. You can make use of the TCL-based user interface to dynamically configure and monitor any registers in this design example.
  • Basic packet checking capabilities of traffic monitor.

Did you find the information on this page useful?

Characters remaining:

Feedback Message