Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 10/21/2021
Public
Document Table of Contents

2.2.5. Hardware Testing

You can compile and test the design using the supported Intel FPGA development kit.

In the Clock Controller application, which is part of the development kit, set the following frequencies:

  • Y1—156.25 MHz
  • U3 (Si5341): OUT2 and OUT3—125 MHz