1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 3. Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for the Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
2.1.4. Compiling and Configuring the Design Example in Hardware
The hardware design example supports physical cable loopback at the E-tile transceiver serial interface. The TX and RX serial data interface, for example, tx_serial_data port and rx_serial_data port need to be connected using a QSFP-DD loopback module.
Note: You must perform an IOPLL IP upgrade for the 10/100/1000Mb Ethernet MAC (Fifoless) with IEEE1588v2 and 2XTBI PCS with E-Tile GXB Transceiver design example. To generate the design example and regenerate the four IOPLL IP components, perform the steps in the Updating IOPLL IP Design File Names section. For more information, refer to KDB link: Why do I need to perform the IOPLL Intel® FPGA IP Upgrade in the Intel® Stratix® 10 E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example?.
To compile the hardware design example and configure it on your Intel® Stratix® 10 device, follow these steps:
- Ensure hardware design example generation is complete.
- In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_dir>/hardware_test_design/altera_eth_top.qpf .
- On the Processing menu, click Start Compilation.
- After a successful compilation, a.sof file is available in <design_example_dir>/hardwarde_test_design directory. Follow these steps to program the hardware design example on the Intel® Stratix® 10 device:
- On the Tools menu, click Programmer.
- In the Programmer, click Hardware Setup.
- Select a programming device.
- Select and add the Stratix 10 E- Tile TX Transceiver Signal Integrity Development Kit to which your Intel Quartus Prime Pro Edition session can connect.
- Ensure that Mode is set to JTAG.
- Select the device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
- In the row with your .sof, check the box for the .sof.
- Check the box in the Program/Configure column.
- Click Start.
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