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1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
3. Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
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2.2.7. Configuration Registers
You can access the 32 bit configuration registers of the design components through the Avalon® memory-mapped interface.
Byte Offset | Block |
---|---|
0x01_0000 | TOD master |
0x02_7800 | TOD TX |
0x02_7900 | TOD RX |
0x02_8000 | Triple-Speed Ethernet Intel® FPGA IP |
0x10_0000 | Traffic Controller |
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