Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 10/21/2021
Document Table of Contents

2.2.7. Configuration Registers

You can access the 32 bit configuration registers of the design components through the Avalon® memory-mapped interface.
Table 11.  Register Map
Byte Offset Block
0x01_0000 TOD master
0x02_7800 TOD TX
0x02_7900 TOD RX
0x02_8000 Triple-Speed Ethernet Intel® FPGA IP
0x10_0000 Traffic Controller

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