Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

ID 683551
Date 4/30/2024
Document Table of Contents

1.1.4. Compiling and Configuring the Design Example in Hardware

The hardware design example supports physical cable loopback at the E-tile transceiver serial interface. The TX and RX serial data interface, for example, tx_serial_data port and rx_serial_data port need to be connected using a QSFP-DD loopback module.
Note: Refer to Test Procedure for the patch required to perform the hardware test for Quartus® Prime Pro Edition software version 21.1.

To compile the hardware design example and configure it on your Stratix® 10 device, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Quartus® Prime Pro Edition software, open the Quartus® Prime project <design_example_dir>/hardware_test_design/altera_eth_tse_hw.qpf .
  3. On the Processing menu, click Start Compilation.
  4. After a successful compilation, a.sof file is available in <design_example_dir>/hardwarde_test_design directory. Follow these steps to program the hardware design example on the Stratix® 10 device:
    1. On the Tools menu, click Programmer.
    2. In the Programmer, click Hardware Setup.
    3. Select a programming device.
    4. Select and add the Stratix 10 E- Tile TX Transceiver Signal Integrity Development Kit to which your Quartus® Prime Pro Edition session can connect.
    5. Ensure that Mode is set to JTAG.
    6. Select the device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.