Triple-Speed Ethernet Stratix® 10 FPGA IP Design Example User Guide

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ID 683551
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 3. Triple-Speed Ethernet Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for the Triple-Speed Ethernet Stratix® 10 IP Design Example User Guide
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Triple-Speed Ethernet IP Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Triple-Speed Ethernet IP Design Example Testbench 2.1.4. Compiling and Configuring the Design Example in Hardware
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.1.3. Simulating the Triple-Speed Ethernet IP Design Example Testbench x
2.1.3.1. Procedure
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Hardware Testing 2.2.6. Interface Signals 2.2.7. Configuration Registers
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clocking Scheme
2.2.5. Hardware Testing x
2.2.5.1. Test Procedure
2.2.7. Configuration Registers x
2.2.7.1. Register Access Definition 2.2.7.2. Triple-Speed Ethernet Register Map 2.2.7.3. Traffic Controller Register Map 2.2.7.4. TOD Register Map
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
3. Triple-Speed Ethernet Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for the Triple-Speed Ethernet Stratix® 10 IP Design Example User Guide

1.2.5.1. Test Procedure

After you compile the Triple-Speed Ethernet IP design example and configure it on your Stratix® 10 device, you can use the System Console to program the IP.

To turn on the System Console and test the hardware design example, follow these steps:

  1. In the Quartus® Prime Pro Edition software, select Tools > In-System Source and Probes Editor to open the default source and probe GUI.
  2. Select Device as indicated in In-System Sources and Probes Editor.
  3. Click File to select the .sof file and click Program Device.
  4. The initial value of source[0] is 0. Click on the value in the Data column to change the value to 1 to release the design from reset mode.
    Figure 9. In-System Sources and Probes Editor
  5. Once the design is out of reset, in the Quartus® Prime Pro Edition software, select Tools > System Debugging Tools>System Console to launch the system console.
  6. In the Tcl Console pane, type cd hwtest/sc to change directory to <design_example_dir>/hardware_test_design/hwtest/sc/.
  7. Type source basic/basic.tcl.
  8. Type list_jtag to display a list of JTAG master indexes that are connected to your board.
  9. Type set_jtag<number_of_appropriate_JTAG_master> to select the JTAG master.
  10. Type source hwtest_main.tcl to run the design example in 10 Mbps, 100 Mbps and 1 Gbps Ethernet speed.
A successful test run displays the following message:
Level Two Title