Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 6/09/2025
Public

Visible to Intel only — GUID: zki1647302799825

Ixiasoft

Document Table of Contents

2.1.1. H-Tile MCDMA IP - Design Examples for Endpoint

Table 3.  H-Tile MCDMA IP - Design Examples for Endpoint
Design Example MCDMA Settings Driver Support App Support
User Mode Interface Type
AVMM DMA

Multi-Channel DMA

AVMM

Custom

Perfq app

DPDK

Mcdma_test

BAM + MCDMA

Custom Perfq app
DPDK Mcdma_test

BAM + BAS + MCDMA

Custom Perfq app
DPDK Mcdma_test
Device-side Packet Loopback

Multi-Channel DMA

AVST 1 Port

Custom

Perfq app

DPDK

Mcdma_test

Netdev

Netdev_app

BAM + MCDMA

Custom Perfq app
DPDK Mcdma_test
Netdev Netdev_app

BAM + BAS + MCDMA

Custom

Perfq app

DPDK

Mcdma_test

Netdev

Netdev_app
Packet Generate/Check

Multi-Channel DMA

Custom

Perfq app

DPDK

Mcdma_test

BAM + MCDMA

Custom Perfq app
DPDK Mcdma_test

BAM + BAS + MCDMA

Custom

Perfq app

DPDK

Mcdma_test
PIO using MQDMA Bypass Mode

Multi-Channel DMA

AVMM

AVST 1 Port

Custom

Perfq app

DPDK

Mcdma_test

BAM + MCDMA

BAM + BAS + MCDMA

Custom Perfq app
DPDK Mcdma_test
Bursting Master

BAM + BAS

n/a

Custom

Perfq app

DPDK

Mcdma_test
Traffic Generator/Checker BAM + BAS n/a

Custom

Perfq app

DPDK

Mcdma_test
Note:
  1. MCDMA H-Tile design example supports SR-IOV with only 1 PF and its VFs for simulation in these configurations.
  2. Netdev driver supports 4 PFs and 1 channel per PF.

For information about supported simulators, refer to Supported Simulators.