Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683517
Date 6/09/2025
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Design Example Detailed Description 3. Design Example Quick Start Guide 4. Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide
1. Introduction x
1.1. Terms and Acronyms 1.2. MCDMA IP Modes
2. Design Example Detailed Description x
2.1. Design Example Overview 2.2. PIO using MCDMA Bypass Mode 2.3. Avalon-ST Packet Generate/Check 2.4. Avalon-ST Device-side Packet Loopback 2.5. Avalon-MM DMA 2.6. BAM_BAS Traffic Generator and Checker 2.7. External Descriptor Controller
2.1. Design Example Overview x
2.1.1. H-Tile MCDMA IP - Design Examples for Endpoint 2.1.2. P-Tile MCDMA IP - Design Examples for Endpoint 2.1.3. F-Tile MCDMA IP - Design Examples for Endpoint 2.1.4. R-Tile MCDMA IP - Design Examples for Endpoint 2.1.5. Design Example BAR Mappings 2.1.6. Design Example Driver Support
2.2. PIO using MCDMA Bypass Mode x
2.2.1. Avalon-ST PIO using MCDMA Bypass Mode 2.2.2. Avalon-MM PIO using MCDMA Bypass Mode
2.2.1. Avalon-ST PIO using MCDMA Bypass Mode x
2.2.1.1. Single-Port Avalon-ST PIO using MCDMA Bypass Mode
2.2.2. Avalon-MM PIO using MCDMA Bypass Mode x
2.2.2.1. Simulation Results 2.2.2.2. Hardware Test Results
2.3. Avalon-ST Packet Generate/Check x
2.3.1. Single-Port Avalon-ST Packet Generate/Check
2.3.1. Single-Port Avalon-ST Packet Generate/Check x
2.3.1.1. Simulation Waveforms 2.3.1.2. Simulation Log 2.3.1.3. Hardware Test Result
2.4. Avalon-ST Device-side Packet Loopback x
2.4.1. Simulation Results 2.4.2. Hardware Test Results
2.5. Avalon-MM DMA x
2.5.1. Simulation Results 2.5.2. Hardware Test Results
2.6. BAM_BAS Traffic Generator and Checker x
2.6.1. BAM_BAS Traffic Generator and Checker Example Design Register Map
2.7. External Descriptor Controller x
2.7.1. Registers 2.7.2. Hardware Test Results
2.7.1. Registers x
2.7.1.1. GCSR Registers (Base address 64’h00000) 2.7.1.2. QCSR Registers(Base address 64’h10000)
3. Design Example Quick Start Guide x
3.1. Design Example Directory Structure 3.2. Generating the Example Design using Quartus® Prime 3.3. Simulating the Design Example 3.4. Compiling the Example Design in Quartus® Prime 3.5. Running the Design Example Application on a Hardware Setup
3.2. Generating the Example Design using Quartus® Prime x
3.2.1. Procedure
3.3. Simulating the Design Example x
3.3.1. Testbench Overview 3.3.2. Supported Simulators 3.3.3. Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example 3.3.4. Run the Simulation Script 3.3.5. Steps to Run the Simulation 3.3.6. View the Results
3.3.5. Steps to Run the Simulation x
3.3.5.1. Steps to Run the Simulation : QuestaSim* / Questa* Intel® FPGA Edition 3.3.5.2. Steps to Run the Simulation : VCS* / VCS* MX 3.3.5.3. Steps to Run the Simulation : Xcelium*
3.5. Running the Design Example Application on a Hardware Setup x
3.5.1. Hardware Requirements 3.5.2. Software Requirements 3.5.3. Set Up the Hardware and Program the FPGA 3.5.4. Configuration Changes from BIOS 3.5.5. Host Operating System Check for Ubuntu v22.04 3.5.6. Installing the Required Kernel Version for Ubuntu v24.04 3.5.7. Set the Boot Parameters 3.5.8. MCDMA Custom Driver 3.5.9. MCDMA DPDK Poll Mode Driver 3.5.10. MCDMA Kernel Mode Network Device Driver
3.5.8. MCDMA Custom Driver x
3.5.8.1. Prerequisites 3.5.8.2. PIO Test 3.5.8.3. DMA Test 3.5.8.4. BAM Test 3.5.8.5. BAS Test
3.5.8.1. Prerequisites x
3.5.8.1.1. Install the Linux Kernel Driver 3.5.8.1.2. Enable Virtual Function 3.5.8.1.3. Build and Install the User Space Library 3.5.8.1.4. Build the Reference Application
3.5.8.2. PIO Test x
3.5.8.2.1. Custom PIO Read Write Test
3.5.8.3. DMA Test x
3.5.8.3.1. Avalon-MM DMA (AVMM DMA) 3.5.8.3.2. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback) 3.5.8.3.3. Avalon-ST Packet Generate/Check (Packet Generate/Check) 3.5.8.3.4. External Descriptor Controller
3.5.8.3.2. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback) x
3.5.8.3.2.1. DMA Test Beyond 256 Channels
3.5.8.3.3. Avalon-ST Packet Generate/Check (Packet Generate/Check) x
3.5.8.3.3.1. DMA Test Beyond 256 Channels
3.5.9. MCDMA DPDK Poll Mode Driver x
3.5.9.1. Prerequisites 3.5.9.2. PIO Test 3.5.9.3. DMA Test 3.5.9.4. BAM Test 3.5.9.5. BAS Test
3.5.9.1. Prerequisites x
3.5.9.1.1. Install the PMD Driver 3.5.9.1.2. Bind the Device 3.5.9.1.3. Enable Virtual Function
3.5.9.3. DMA Test x
3.5.9.3.1. Avalon-MM DMA (AVMM DMA) 3.5.9.3.2. Avalon-ST Packet Generate/Check (Packet Generate/Check) 3.5.9.3.3. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback)
3.5.9.3.2. Avalon-ST Packet Generate/Check (Packet Generate/Check) x
3.5.9.3.2.1. DMA Test Beyond 256 Channels
3.5.9.3.3. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback) x
3.5.9.3.3.1. DMA Test Beyond 256 Channels
3.5.10. MCDMA Kernel Mode Network Device Driver x
3.5.10.1. Prerequisites 3.5.10.2. PIO Test 3.5.10.3. Ping Test
3.5.10.1. Prerequisites x
3.5.10.1.1. Build and Install Netdev Driver 3.5.10.1.2. Enable Virtual Function
1. Introduction
2. Design Example Detailed Description
3. Design Example Quick Start Guide
4. Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide

2.1.6. Design Example Driver Support

The table below summarizes the driver support for the MCDMA design example variants. It uses the following acronyms:

  • User Space I/O (UIO): A kernel base module that the PCIe device uses to expose its resources to the user space.
  • Virtual Function I/O (VFIO) driver: An IOMMU/device-agnostic framework for exposing direct device access to the user space in a secure, IOMMU-protected environment.
  • Data Plane Development Kit (DPDK): Consists of libraries to accelerate packet processing workloads running on a wide variety of CPU architectures.
Table 8.  Driver Support for MCDMA Design Examples
Parameter Custom Driver DPDK Driver Kernel Mode Netdev Driver
Description Also known as the user mode driver, this driver is created to support both UIO and VFIO base kernelmodules. This driver provides custom APIs and can be used without depending on any framework. This DPDK Poll Mode Driver (PMD) uses the DPDK framework. The PMD will expose the device as an ethernet device. It supports both UIO and VFIO base kernel modules. Existing DPDK applications can be integrated with the MCDMA PMD. Kernel Mode Netdev Driver exposes the MCDMA IP as a Network Device and enables standard applications to perform network data transfers using the Linux network stack.
Directory/Driver Path <example_design>/pX_software/user <example_design>/pX_software/dpdk <example design>/pX_software/kernel/
SR-IOV Support Yes Yes Yes
Multi channel DMA Avalon-MM DMA Design Example Yes, up to 2K Channels Yes, up to 2K Channels No
Multi channel DMA Avalon-MM DMA with SRIOV Design Example Yes, up to 2K Channels Yes, up to 2K Channels No
BAM+BAS+MCDMA Avalon-MM DMA Design Example Yes, up to 2K Channels Yes, up to 2K Channels No
BAM+BAS+MCDMA Avalon-MM DMA with SR-IOV Design Example Yes, up to 2K Channels Yes, up to 2K Channels No
Multi channel DMA Avalon-MM PIO using MQDMA Bypass Mode Design Example Yes Yes No
Multi channel DMA Avalon-ST 1-port PIO using MQDMA Bypass Mode Design Example Yes Yes Yes
BAM+BAS+MCDMA Avalon-MM PIO using MQDMA Bypass Mode Design Example Yes Yes No
BAM+BAS+MCDMA Avalon-ST 1-Port PIO using MQDMA Bypass Mode Design Example Yes Yes No
Bursting Master PIO using MQDMA Bypass Mode Design Example Yes Yes No
Bursting Slave PIO using MQDMA Bypass Mode Design Example Yes Yes No
BAM+BAS PIO using MQDMA Bypass Mode Design Example Yes Yes No
Data Mover Only PIO using MQDMA Bypass Mode Design Example Yes No No
Multi channel DMA Avalon 1-port Device-side Packet Loopback Design Example Yes Yes, 256 channels Yes, support 4 PFs, 64 channel per PF
Multi channel DMA Avalon 1-port Device-side Packet Loopback with SRIOV Design Example Yes Yes, 256 channels No
Multi channel DMA Avalon1-port Packet Generate/ Check Design Example Yes Yes, 256 channels No
Multi channel DMA Avalon 1-port Packet Generate/ Check with SR-IOV Design Example Yes No No
BAM+BAS Traffic Generator/Checker Design Example Yes Yes No
Data Mover Only External Descriptor Controller Design Example Yes No No
Note:

The software directory is created multiple times depending on the Hard IP mode selected (1x16, 2x8 or 4x4) for Quartus® Prime Pro Edition v23.3 onwards.

The p0_software folder is generated for the 1x16 Hard IP mode.

The p1_software folder is generated for the 2x8 Hard IP mode.

The p2_software and p3_software folders are generated only for the 4x4 Hard IP mode.

Note: You must use the corresponding software folder with each IP port.
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