AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel® Cyclone® 10 GX FPGA Development Board

ID 683454
Date 11/11/2019
Public
Document Table of Contents

3.6. Step 6: Verifying Hardware with Signal Tap

  1. In the Signal Tap window, click File > Open, and open stp_core_partition_reuse.stp.
  2. Ensure that the development kit is powered ON and connected to the machine from which you open the Signal Tap logic analyzer.
  3. Set up the JTAG Chain Configuration, and ensure Instance Manager is Ready to acquire.
  4. As trigger condition, select db_count_24, right click the column under Trigger Conditions, and set to Falling Edge.
  5. Run analysis by clicking Processing > Run Analysis.
    When the analysis finishes, the Waveform tab shows the captured data.
Figure 29. Captured Data in Waveform Tab
  • db_value_0 and db_count_24 signals behaves identically to the Developer flow tutorial.
  • The db_value_0 changes as per db_count_24 a cycle later.
  • The db_value_* and db_count_* are the partition boundary ports from the imported partition.
  • db_count_0, db_count_1 and db_count_2 signals show the transition of the counter inside the imported partition.
  • The count[0], count[1], count[2] signals show the transition of another counter in the parent partition during this process.

Did you find the information on this page useful?

Characters remaining:

Feedback Message