AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel® Cyclone® 10 GX FPGA Development Board

ID 683454
Date 11/11/2019
Public
Document Table of Contents

3.2. Step 2: Creating a Signal Tap File

Create a Signal Tap file that includes partition boundary ports from the reused core partition.
  1. Click Tools > Signal Tap Logic Analyzer.
  2. In the Signal Tap logic analyzer GUI, click auto_signaltap_0.
  3. In the Setup tab, double-click to launch the Node Finder.
  4. In the Node Finder, type * in the Named field, set Filter to Signal Tap: pre-synthesis, and then click Search.
    Figure 24. Node Finder Search
    The Matching Nodes list shows signals that match the search criteria.
  5. Add the boundary ports from the imported partition (db_*) from u_blinking_led_top to the Nodes Found list.

    The names must match what appears in the Developer project's report file.

    Figure 25. Node Finder
    Note: If you add nodes other than the db_* nodes from the imported partition, the Compiler leaves them unconnected.
  6. Add nodes count[2:0] from the root partition to the Nodes Found list, and click Insert.
  7. Configure the Signal Tap acquisition. Refer to Step 6: Creating a Signal Tap File (Optional) for details.
    Figure 26. Specifying the Clock Source
  8. Click File > Save, and save the file as stp_core_partition_reuse.stp.
    A dialog box appears asking if you want to enable Signal Tap file for the project.
  9. Click Yes, and close the file.

Did you find the information on this page useful?

Characters remaining:

Feedback Message