AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel® Cyclone® 10 GX FPGA Development Board

ID 683454
Date 11/11/2019
Public
Document Table of Contents

4.4. Step 4: Generating HDL Instance of Signal Tap

  1. From the IP Catalog (Tools > IP Catalog), select and double-click the Signal Tap Logic Analyzer Intel® FPGA IP . Set the name as stp_root_partition.
  2. In the IP Parameter Editor, change Data Input Port Width to 6 and Trigger Input Port Width to 6.
    Figure 32.  Signal Tap Logic Analyzer Intel® FPGA IP Parameter Editor
  3. Generate the IP.
  4. In the top.sv file, uncomment lines 45 to 49, and save the file.

    This action instantiates the HDL Signal Tap logic analyzer in the root partition.

    Lines 45 to 49:
    // stp_root_partition stp_root_partition inst (
    //   .acq_clk (clock),// input, width=1, acq_clk.clk
    //   .acq_data_in \
    //      ({top_LED, count[3:0]}),// input, width=4, tap.acq_data_in
    //   .acq_trigger_in \
    //      ({top_LED, count[3:0]})// input, width=4, tap.acq_trigger_in
    //   );

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