AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel® Cyclone® 10 GX FPGA Development Board

ID 683454
Date 11/11/2019
Public
Document Table of Contents

4.1. Step 1: Creating a Reserved Core Partition and Defining a Logic Lock Region

  1. c10_pcie_devkit_design_block_reuse_stp/Root_Partition_Reuse/Developer/top.qpf project file.
  2. On the Compilation Dashboard, click Analysis & Synthesis to synthesize the design. When synthesis is complete, the Compilation Dashboard displays a check mark.
  3. In the Project Navigator, right-click the u_blinking_led_top instance in the Hierarchy tab, and then click Design Partition > Reserved Core. A design partition icon appears next to each instance you assign.
    Note: If the Design Partition Window is not visible on the GUI, click Assignments > Design Partitions Window.
    Figure 30. Set Reserved Core Partition Type
  4. Right-click the u_blinking_led_top instance in the Project Navigator, and click Logic Lock Region > Create New Logic Lock Region.
  5. To modify the region properties, click Assignments > Logic Lock Regions Window.
  6. Change the Width to 123, and the Height to 61.
  7. In the Origin column, specify X63_Y102.
  8. Enable the Reserved and Core-Only options.
  9. In the Size/State column, specify Fixed/Locked.
  10. Click the Routing Region cell. The Logic Lock Routing Region Settings dialog box appears.
  11. Specify Fixed with expansion with Expansion Length of 0 for the Routing Type. The actual size and location are arbitrary for this tutorial. However, you can view and adjust the Logic Lock Region shape in the Chip Planner.
  12. Click the <<new>> cell and then repeat steps 5 through 12 to create an empty_region with the following properties:
    • Width of 103 and Height of 1.
    • Origin of X20_Y20.
    • Reserved and Core-Only are On.
    • Size/State of Fixed/Locked.
    • Routing Region is Unconstrained.
    Figure 31.  Logic Lock Regions Window

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