AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel® Cyclone® 10 GX FPGA Development Board

ID 683454
Date 11/11/2019
Public
Document Table of Contents

5.5. Step 5: Verifying the Hardware of Reserved Core Partition with Signal Tap

To use Signal Tap GUI for the reserved core:
  1. Determine the bridge index according to the number in the synthesis report file (Root_Partition_Reuse/Developer/output_files/top.syn.rpt), under JTAG Bridge Agent Instance Information in the Developer project.
    Figure 37. Synthesis Report
  2. In the Signal Tap window, click File > Open, and open stp_periphery_reuse_core.stp.
  3. Ensure that the development kit is powered ON and connected to the machine from which you open the Signal Tap logic analyzer.
  4. Set up the JTAG Chain Configuration, and ensure Instance Manager is Ready to acquire.
  5. Set the Bridge Index as found in the synthesis report (Root_Partition_Reuse/Developer/output_files/top.syn.rpt in the Developer Project
    If the values for Bridge Index are different, Signal Tap reports Instance not found.
    Figure 38. Setting the Bridge Index
  6. To set the trigger condition, select count[24], right click the column under Trigger Conditions and select Falling Edge.
    Figure 39. Trigger Conditions
  7. Run analysis by clicking Processing > Run Analysis.
    When the analysis finishes, the Waveform tab shows the captured data.
  8. Verify the transition of reserved core nodes in Signal Tap GUI. The expected behavior is:
    • value_top[0] transitions along with count[24].
    • count[0], count[1], and count[2] show the transition of other counter bits in the reserved core partition during this process.
    Figure 40. Waveforms for reserved core Partition Nodes in Consumer Project

Did you find the information on this page useful?

Characters remaining:

Feedback Message