AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel® Cyclone® 10 GX FPGA Development Board

ID 683454
Date 11/11/2019
Public
Document Table of Contents

3.5. Step 5: Programming the Device and Verifying the Hardware

You can now verify the results of the Core Partition Reuse—Consumer tutorial module on the hardware.
  1. Program the device, as Step 7: Programming the Device and Verifying the Hardware describes.
  2. After programming is complete, verify the following:
    • LEDs D21-D20 map to the blinking_led_top core
    • LEDs D19-D22 map to the top-level (root) design
    After configuring the FPGA, the blinking_led_top core flashes LEDs in binary order. The top-level design shows a shifting bit in green.

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