AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel® Cyclone® 10 GX FPGA Development Board

ID 683454
Date 11/11/2019
Public
Document Table of Contents

2.4. Step 4: Exporting the Core Partition and Creating the Black Box File

After compilation, you export the core partition and create a supporting black box port definitions file. This tutorial reuses the final compilation snapshot.
  1. Click Project > Export Design Partition. Select blinking_led_top for the Partition name, and the final Snapshot for export.
  2. Confirm blinking_led_top.qdb as the Partition Database File name, and then click OK. The final blinking_led.qdb that you export preserves the placement and routing information from the Developer project reused in the Consumer project.
  3. To create the black box file, click File > New, select SystemVerilog HDL File under Design Files, and then click OK.
    A blank .sv file opens to allow you to enter the port definitions for the partition you export and the partition boundary ports created in Step 3: Compiling and Checking Debug Nodes.
  4. Include any Verilog parameters or VHDL generics in the definition. The port definitions in the black box file must look just like the original, without the logic RTL.
    module blinking_led_top(
    	output [3:0] value,
    	input clock,
    	output db_count_0,
    	output db_count_1,
    	output db_count_2,
    	output db_count_24,
    	output db_value_0,
    	output db_value_1,
    	);
    
    endmodule
  5. Save the black box file as blinking_led_top_bb.sv. When saving this file, turn off the option to Add file to current project.

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