AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel® Cyclone® 10 GX FPGA Development Board

ID 683454
Date 11/11/2019
Public
Document Table of Contents

4.5. Step 5: Compiling Export Root Partition and Copying Files to Consumer Project

When you export the root partition, you include all resources outside of the reserved core partition. The logic inside the reserved core, including the SLD JTAG Bridge Host, are not exported.

  1. Click Compile Design on the Compilation Dashboard.
  2. To export the root partition to a .qdb file, click Project > Export Design Partition. Select root_partition for the Partition name, final for Snapshot and turn on Include entity-bound SDC files for the selected partition:
    Figure 33. Export Design Partition
  3. Copy the root_partition.qdb and top.sdc files to the Root_Partition_Reuse/Consumer/ directory.
    When you include entity bound .sdc files with the partition export, you need to only copy the top-level .sdc file, which is not bound to an entity. The top-level design uses constraints for analysis only, and does not drive any logic or routing.

When reusing the root partition, the Consumer integrates the root_partition.qdb and top.sdc files into the Consumer project. The Consumer can also include a separate .sdc file to constrain the logic that they use in the reserved core partition.

The Logic Lock (Standard) boundary is visible in the Chip Planner in the Consumer project for reference only. The Consumer cannot modify this region.

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