AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel® Cyclone® 10 GX FPGA Development Board

ID 683454
Date 11/11/2019
Public
Document Table of Contents

5.3. Step 3: Synthesizing, Creating Signal Tap File, and Compiling

  1. On the Compilation Dashboard, click Analysis & Synthesis to synthesize the design. When synthesis is complete, the Compilation Dashboard displays a check mark.
  2. In the Project Navigator, right-click the u_blinking_led_top instance in the Hierarchy tab, and then click Design Partition > Default.
    Important: root_partition.qdb contains the information about u_blinking_led_top from Developer project. It is not necessary to set the partition type to Reserved Core and create the Logic Lock Region for it.
  3. In the Intel® Quartus® Prime Pro Edition software, click Tools > Signal Tap Logic Analyzer.
  4. In the Instance Manager, click auto_signaltap_0.
  5. In the Setup tab, double-click to launch the Node Finder.
  6. In the Node Finder, type * in the Named field, set Filter to Signal Tap: pre-synthesis, and then click Search.
  7. In the Matching Nodes list, expand the u_blinking_led_top|count.
  8. Select count[0], count[1], count[2], and count[24]. Insert the nodes by clicking >.
  9. Select value_top under u_blinking_led_top. Click >, then click Insert, and then click Close.
  10. In the Signal Tap window, under Signal Configuration, click () next to the Clock field.
  11. In the Node Finder, search for *, and select the clock node in the reserved core partition u_blinking_led_top. Click >, and then click OK to close.
  12. Leave all the other options as default under Signal Configuration. Go to File > Save and save the file as stp_periphery_reuse_core.stp.
    A dialog box appears asking if you want to enable Signal Tap file for the project.
  13. Click Yes, and close the file.
  14. Click Compile Design on the Compilation Dashboard.

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