4. Root Partition Reuse Debug—Developer
The Developer adds bridge components to enable debug of the reserved core partition, and adds a Signal Tap HDL instance to debug the root partition. Then, the Developer compiles and exports the root partition, including logic and periphery resources, and finally, copies the root_partition .qdb and .sdc files to the Consumer project.
Completed Tutorial Files
In the c10_pcie_devkit_design_block_reuse_stp folder, the Root_Partition_Reuse/Completed/Developer/ directory contains the completed files for this tutorial module.
This tutorial module includes the following steps:
- Step 1: Creating a Reserved Core Partition and Defining a Logic Lock Region
- Step 2: Generating and Instantiating SLD JTAG Bridge Agent in the Root Partition
- Step 3: Generating and Instantiating the SLD JTAG Bridge Host
- Step 4: Generating HDL Instance of Signal Tap
- Step 5: Compiling Export Root Partition and Copying Files to Consumer Project
- Step 6: Programming the Device and Verifying the Hardware
- Step 7: Generating a Signal Tap File for the Root Partition
- Step 8: Verifying the Hardware with Signal Tap
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