AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel® Cyclone® 10 GX FPGA Development Board

ID 683454
Date 11/11/2019
Document Table of Contents

4.3. Step 3: Generating and Instantiating the SLD JTAG Bridge Host

  1. From the IP Catalog (Tools > IP Catalog), select and generate the SLD JTAG Bridge Host Intel® FPGA IP . Set the name as debug_host.
    For details about generating the SLD JTAG Bridge Host Intel® FPGA IP, refer to the Intel® Quartus® Prime Pro Edition User Guide: Debug Tools .
  2. Open the file, uncomment the lines 25 to 30 and 41 to 48, and save the file.
    This action instantiates the SLD JTAG Bridge Host in the Reserved Core partition, connecting the debug fabric to the parent partition.

    Lines 25 to 30:

    //		input wire tck (tck),		 // connect_to_bridge_host .tck
    //		input wire tms (tms),		 // .tms
    //		input wire tdi (tdi),	 	// .tdi
    //		input wire vir_tdi (vir_tdi), // .vir_tdi
    //		input wire ena (ena),		 // .ena
    //		output wire tdo (tdo)		 // .tdo  

    Lines 41 to 48:

    //   debug_host debug_host_inst ( 
    //      .tck (tck),   //input, width=1, connect_to_bridge_host .tck
    //      .tms (tms),   //input, width=1, .tms
    //      .tdi (tdi),   //input, width=1, .tdi
    //      .vir_tdi (vir_tdi), //input, width=1, .vir_tdi
    //      .ena (ena),    //input, width=1, .ena
    //      .tdo ()        //output, width=1, .tdo
    //      );