AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel® Cyclone® 10 GX FPGA Development Board

ID 683454
Date 11/11/2019
Public
Document Table of Contents

2.1. Step 1: Creating a Core Partition

During this step, you open the project, run synthesis, and define a design partition for the core logic.
  1. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project, and open the c10_pcie_devkit_design_block_reuse_stp/Core_Partition_Reuse/Developer/top.qpf project file.
  2. On the Compilation Dashboard, click Analysis & Synthesis to synthesize the design. When synthesis is complete, the Compilation Dashboard displays a check mark.
    Figure 7. Compilation Dashboard
  3. In the Project Navigator, right-click the u_blinking_led_top instance in the Hierarchy tab, and then click Design Partition > Default. A design partition icon appears next to each instance you assign.
    Figure 8. Create Design Partition
    Note: If the Design Partition Window is not visible on the GUI, click Assignments > Design Partitions Window.

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