AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel® Cyclone® 10 GX FPGA Development Board

ID 683454
Date 11/11/2019
Public
Document Table of Contents

4.2. Step 2: Generating and Instantiating SLD JTAG Bridge Agent in the Root Partition

  1. From the IP Catalog (Tools > IP Catalog), select and generate the SLD JTAG Bridge Agent Intel® FPGA IP . Set the name as debug_agent.
    For details about generating the SLD JTAG Bridge Agent Intel® FPGA IP, refer to the Intel® Quartus® Prime Pro Edition User Guide: Debug Tools .
  2. Open the top.sv file, uncomment lines 56 to 65 and 74 to 79, and save the file.
    This action instantiates the SLD JTAG Bridge Agent in the root partition.

    Lines 56 to 65:

    //   wire tck, tms, tdi, vir tdi, ena, tdo; 
    //   debug_agent debug_agent_inst ( 
    //      .tck (tck), //output, width=1, connect_to_bridge_host .tck
    //      .tms (tms), //output, width=1,        .tms
    //      .tdi (tdi), //output, width=1,        .tdi
    //      .vir_tdi (vir_tdi),//output, width=1, .vir_tdi
    //      .ena (ena),  //output, width=1,       .ena
    //      .tdo (tdo)   // input, width=1,       .tdo
    //      );

    Lines 74 to 79:

    //   .tck (tck),   //input,  width=1, connect_to_bridge_host .tck
    //   .tms (tms),   //input,  width=1,        .tms
    //   .tdi (tdi),   //input,  width=1,        .tdi
    //   .vir_tdi (vir_tdi), //input,  width=1,  .vir_tdi
    //   .ena (ena),      //input,  width=1,     .ena
    //   .tdo (tdo)      //output, width=1,      .tdo

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