Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Public
Document Table of Contents

3.6. Signals

Figure 31. Top-level Signals for Intel® Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
Table 10.  Design Example Interface Signals
Signal Direction Width Description
Clock and Reset Signal
mgmt_clk Input 1
Input clock for:
  • Avalon® memory-mapped PHY management interface for Serial Lite III Streaming IP core
  • Demo management module
  • Demo control module
  • Transceiver reset controller
pll_ref_clk Input 1

This reference clock is used by the Clock Data Recovery (CDR) unit in the transceiver. It serves as a reference for the CDR to recover the clock from the serial line. The frequency of this clock must match the frequency you select in the IP parameter editor. It should also match the frequency of the tx_pll_ref_clk reference clock for the TX PLL at the Source variant.

mgmt_reset_n Input 1

Design example asynchronous master reset. Assert this reset signal to reset the overall design example system.

This is an active low signal.

snk_core_reset_n Output 1

Demo management module asserts this signal to reset traffic checker module.

src_core_reset_n Output 1

Demo management module asserts this signal to reset traffic generator module.

Data Signal
rx[n] Input Based on Number of Lanes value

This vector carries the transmitted streaming data from the core.

n represents the number of lanes.

tx[n] Output Based on Number of Lanes value

This vector carries the transmitted streaming data to the core.

n represents the number of lanes.

Status Signal
rx_activity_n Output 1

This single bit signal indicates that the data is valid.

tx_activity_n Output 1

This single bit signal indicates that the data is valid.

snk_link_up_n Output 1

The core asserts this signal to indicate that the core initialization is complete and is ready to receive user data.

src_link_up_n Output 1

The core asserts this signal to indicate that the core initialization is complete and is ready to transmit user data.