Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Document Table of Contents

2.1. Features

Features for Standard Clocking Mode design example includes:
  • Support up to 12 lanes for 17.4 Gbps and 4 lanes for 28 Gbps transceiver data rate
  • Support for simplex and duplex transmission mode
  • Traffic checker for data verification and lane de-skew verification
  • Support for CRC error injection using Nios® II processor
  • Slave test mode for master and slave testing