Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Document Table of Contents

5. Detailed Description for Intel® Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example

This design example demonstrates the functionality of data streaming using advanced clocking mode.

To generate the design example, select any of the following presets:

  • Advanced Clocking Mode 4x28.0G
  • Advanced Clocking Mode 2x25.0G
  • Advanced Clocking Mode 6x12.5G
  • Advanced Clocking Mode 6x17.4G

The design examples are available only in duplex mode.

Note: To target the Intel® Stratix® 10 E-tile device with the Intel® Stratix® 10 TX Signal Integrity development kit, make sure to select E-Tile for the Transceiver Tile parameter in the IP tab.