Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Document Table of Contents

4.4.1. Testbench

The generated example testbench is dynamic and has the same configuration as the IP.

Figure 37. Serial Lite III Streaming Example Testbench (Duplex) for Intel® Stratix® 10 E-tile Standard Clocking Mode