Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Document Table of Contents

3.3. Functional Description

The Intel® Stratix® 10 H-tile and L-tile design examples consist of various components. The following block diagrams show the design components and the top level connections of the design examples.

Figure 20. Design Example for Simplex Core in Advanced Clocking Mode
Figure 21. Design Example for Duplex Core in Advanced Clocking Mode