Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021

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Document Table of Contents Nios II Processor Code

The Nios® II processor controls the options exercised in the design example. The code also enables the configuration RAM (CRAM) bits for CRC-32 error injection support.

The design example sets the bit for channel 0 that connects to lane 0 in the design example. Therefore, CRC error injection is exercisable for lane 0 only. Refer to the Nios® II processor source code (demo_control.c) for information on setting bits for other channels.

The demo_control.c program Intel® Stratix® 10 H-tile and L-tile devices uses the control registers to dynamically toggle the rx_seriallpbken port on the Transceiver PHY block to change the TX to RX loopback from internal to external.