Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Document Table of Contents

2.3.1. Design Example Components3.3.1. Design Example Components

The design example consists of the following components:

  • Serial Lite III Streaming IP core variation
  • Source and sink user clock—fPLL
  • Traffic generator
  • Traffic checker
  • Demo control
  • Demo management

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