Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Document Table of Contents

1.4.1. Procedure

To compile and simulate the design:
  1. Change the working directory to <example_design_directory>/ed_sim/<simulator> .
  2. Run the simulation script for the simulator of your choice.
    Simulator Command
    ModelSim* do run_tb.tcl
    VCS* / VCS* MX sh
    Note: This simulator is not supported for Intel® Stratix® 10 E-tile design examples.
    do run_tb.tcl
    Xcelium* sh
    A successful simulation ends with the following message, "Test Passed."
After successful completion, you can analyze the results.