Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Document Table of Contents

5.3.2. Reset Scheme

The mgmt_reset_n reset signal controls the overall reset structure for the design example. This is an asynchronous and active-low signal. Asserting this signal resets the demo control module and the Serial Lite III Streaming IP core. The traffic generator and traffic checker modules get reset through the demo management and the reset synchronizer.

The following diagram shows the reset scheme implemented in the design example.

Figure 42. Reset Scheme for Intel® Stratix® 10 E-tile Serial Lite III Streaming Duplex Core in Advanced Clocking Mode