Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021

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Document Table of Contents

2.5.1. Design Setup

The design example targets the Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit.

The design includes an SDC script as well as a QSF file with verified constraints in loopback mode. If you use the design example with another device or development board, you may need to update the device setting and constraints in the QSF file.