Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Document Table of Contents

4.3. Functional Description

The Intel® Stratix® 10 E-tile design examples consist of various components. The following block diagram shows the design components and the top level connections of the design examples.

Figure 32. Design Example for Duplex Core in Standard Clocking Mode

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