Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683341
Date 11/01/2021
Public
Document Table of Contents

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.3
IP Version 19.3.0
The Serial Lite III Streaming Intel® FPGA IP provides the capability of generating design examples for selected configurations.

The Serial Lite III Streaming Intel® FPGA IP offers eight preset settings for Intel® Stratix® 10 H-tile and L-tile devices in both simplex and duplex modes and Intel® Stratix® 10 E-tile devices in duplex mode.

  • Standard Clocking Mode 6x12.5G
  • Standard Clocking Mode 6x17.4G
  • Standard Clocking Mode 2x25G
  • Standard Clocking Mode 4x28G
  • Advanced Clocking Mode 6x12.5G
  • Advanced Clocking Mode 6x17.4G
  • Advanced Clocking Mode 2x25G
  • Advanced Clocking Mode 4x28G
Figure 1. Development Stages for the Design Example

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