Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Public

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Document Table of Contents

1.2. Design Example Block Diagrams

Figure 3. High-Level Block Diagram for Intel® Stratix® 10 H-tile and L-tile Design Examples
Figure 4. High-Level Block Diagram for Intel® Stratix® 10 E-tile Design Examples