Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Public
Document Table of Contents

5.3.1.5. Demo Control

The demo control module is a Nios® II processor system, generated in Platform Designer (Standard), to control the demo hardware.

Demo control module also consists of a timer to track interrupt occurrence, Avalon® memory-mapped interface to access demo management and the Serial Lite III Streaming Intel® FPGA IP PHY interface, a reset controller, a UART interface, and an Avalon® streaming interface.