Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Document Table of Contents Nios II Processor Code

The Nios® II processor controls the options exercised in the design example. The code also enables CRAM bits for CRC-32 error injection support.

The design example sets the bit for channel 0 that connects to lane 0 in the design example. Therefore, CRC error injection is exercisable for lane 0 only. Refer to the Nios® II processor source code (demo_control.c) for information on setting bits for other channels.

The demo_control.c program for Intel® Stratix® 10 E-tile devices uses the Transceiver PHY dynamic reconfiguration block to control registers to dynamically toggle the Transceiver PHY block seriallpback to change the TX to RX loopback from internal to external. The demo_control program also uses the Transceiver PHY dynamic reconfiguration to enable initial coarse adaptive equalization to reduce bit error during high data rate transmission.