Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683341
Date 11/01/2021
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for Intel® Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example 3. Detailed Description for Intel® Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example 4. Detailed Description for Intel® Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example 5. Detailed Description for Intel® Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example 6. Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 7. Document Revision History for Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Example Block Diagrams 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
1.3. Generating the Design x
1.3.1. Procedure 1.3.2. Design Example Parameters 1.3.3. Presets
1.4. Simulating the Design x
1.4.1. Procedure
2. Detailed Description for Intel® Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Signals
2.3. Functional Description x
2.3.1. Design Example Components 2.3.2. Reset Scheme 2.3.3. Clocking Scheme
2.3.1. Design Example Components x
2.3.1.1. Serial Lite III Streaming IP Core 2.3.1.2. User Clock 2.3.1.3. Traffic Generator 2.3.1.4. Traffic Checker 2.3.1.5. Demo Control 2.3.1.6. Demo Management 2.3.1.7. Nios II Processor Code
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Design Setup 2.5.2. Error Details
3. Detailed Description for Intel® Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Signals
3.3. Functional Description x
3.3.1. Design Example Components 3.3.2. Reset Scheme 3.3.3. Clocking Scheme
3.3.1. Design Example Components x
3.3.1.1. Serial Lite III Streaming IP Core 3.3.1.2. User Clock 3.3.1.3. Traffic Generator 3.3.1.4. Traffic Checker 3.3.1.5. Demo Control 3.3.1.6. Demo Management 3.3.1.7. Nios II Processor Code
3.4. Simulation x
3.4.1. Testbench
3.5. Hardware Testing x
3.5.1. Design Setup 3.5.2. Error Details
4. Detailed Description for Intel® Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Signals
4.3. Functional Description x
4.3.1. Design Example Components 4.3.2. Reset Scheme 4.3.3. Clocking Scheme
4.3.1. Design Example Components x
4.3.1.1. Serial Lite III Streaming IP Core 4.3.1.2. User Clock 4.3.1.3. Traffic Generator 4.3.1.4. Traffic Checker 4.3.1.5. Demo Control 4.3.1.6. Demo Management 4.3.1.7. Nios II Processor Code
4.4. Simulation x
4.4.1. Testbench
4.5. Hardware Testing x
4.5.1. Design Setup 4.5.2. Error Details
5. Detailed Description for Intel® Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Signals
5.3. Functional Description x
5.3.1. Design Example Components 5.3.2. Reset Scheme 5.3.3. Clocking Scheme
5.3.1. Design Example Components x
5.3.1.1. Serial Lite III Streaming IP Core 5.3.1.2. User Clock 5.3.1.3. Traffic Generator 5.3.1.4. Traffic Checker 5.3.1.5. Demo Control 5.3.1.6. Demo Management 5.3.1.7. Nios II Processor Code
5.4. Simulation x
5.4.1. Testbench
5.5. Hardware Testing x
5.5.1. Design Setup 5.5.2. Error Details
1. Quick Start Guide
2. Detailed Description for Intel® Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Intel® Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Intel® Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Intel® Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

5.3.1.7. Nios II Processor Code

The Nios® II processor controls the options exercised in the design example. The code also enables CRAM bits for CRC-32 error injection support.

The design example sets the bit for channel 0 that connects to lane 0 in the design example. Therefore, CRC error injection is exercisable for lane 0 only. Refer to the Nios® II processor source code (demo_control.c) for information on setting bits for other channels.

The demo_control.c program for Intel® Stratix® 10 E-tile devices uses the Transceiver PHY dynamic reconfiguration block to control registers to dynamically toggle the Transceiver PHY block seriallpback to change the TX to RX loopback from internal to external. The demo_control program also uses the Transceiver PHY dynamic reconfiguration to enable initial coarse adaptive equalization to reduce bit error during high data rate transmission.

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