Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Document Table of Contents

5.5.2. Error Details

These are the list of errors reported when you run the design example.
Table 15.  Details of Errors Reported
Error Description
Source Error:
Adaptation FIFO Overflow To indicate source adaptation FIFO overflow error.
Sink Errors:
Loss of Alignment During Normal Operation To indicate loss of alignment error (error_rx[1]).
Meta Frame CRC Errors To indicate CRC errors.
Lane Swap Errors To indicate lane swap errors in traffic checker.
Lane Sequence Errors To indicate lane sequence error in traffic checker.
Lane Alignment Errors To indicate lane alignment error in traffic checker.