100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 9/20/2022
Public

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8.1.3. SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping)

The 100G Interlaken IP core supports a lane reversal feature (lane swapping). Lane swapping parameters determine the order in which blocks are distributed and gathered from the lanes. The 100G Interlaken IP core provides the following two options for the lane order:

  • Straight Lane order. The transmitter sends Interlaken blocks sequentially across the lanes starting with the top lane, ending with Lane 0. The receiver takes in Interlaken blocks starting with the top lane, ending with Lane 0.
Figure 23. Straight Lane Order


  • Swapped Lane order. The transmitter sends Interlaken blocks sequentially across the lanes starting with Lane 0, ending with Lane N. The receiver takes in Interlaken blocks starting with Lane 0, ending with Lane N.
Figure 24. Swapped Lane Order


Two parameters determine lane order:

SWAP_TX_LANES

SWAP_RX_LANES

When a parameter is set to 0, the 100G Interlaken IP core implements the Straight Lane order. When a parameter is set to 1, the 100G Interlaken IP core implements the Swapped Lane order. The TX and RX parameters are independent and can be set separately.

To conform with the Interlaken specification, the default value of SWAP_TX_LANES and SWAP_RX_LANES is 1.

Note: Running traffic with incompatible lane swapping configuration results in CRC24 errors and incorrect data at the receiver.