100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 9/20/2022

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3.6. Enable M20K ECC Support

The Enable M20K ECC support parameter specifies whether your 100G Interlaken IP core variation supports the ECC feature in the Stratix V and Intel® Arria® 10 M20K memory blocks that are configured as part of the IP core. This parameter is relevant only for IP core variations that target a Stratix V device or an Intel® Arria® 10 device.

You can turn this parameter on to enable single-error correct, double-adjacent-error correct, and triple-adjacent-error detect ECC functionality in the M20K memory blocks configured in your IP core. You can turn this parameter off to decrease IP core latency and save resources on the device. If you turn on this feature, you enhance data reliability but increase latency and resource utilization. Without the ECC feature, a single M20K memory block can support a data path width of 40 bits. With the ECC feature, eight of those bits are dedicated to the ECC, and an M20K memory block can support a maximum data path width of 32 bits. Therefore, to support the same data bus width, the Quartus Prime Fitter must configure additional M20K blocks. The ECC check adds latency to the path through the memory block, and increases the amount of device memory used by your IP core.

A checkmark in the check box to the left of the parameter turns this parameter on, specifying that the IP core supports this feature. A check box with no checkmark indicates that the option is turned off, and the IP core does not support this feature.

By default, the Enable M20K ECC support parameter is turned off.