100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 9/20/2022
Public

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5.1. 100G Interlaken IP Core Clock Interface Signals

Table 15.   100G Interlaken IP Core Clock Interface

Signal Name

Direction

Width (Bits)

Description

Clock Ports

pll_ref_clk

Input

1

Transceiver reference clock for the RX CDR PLL in IP core variations that target an Intel® Arria® 10 device. Transceiver reference clock for the RX CDR PLL and the TX transceiver PLL in all other variations.

Table 16.  100G Interlaken IP Core Supported pll_ref_clk FrequenciesThe sets of valid frequencies vary with the per-lane data rate of the transceivers.

Per-Lane Data Rate

Valid pll_ref_clk Frequencies (MHz)

10.3125

206.25, 257.8125, 322.265625, 412.5, 515.625, 644.53125

12.5, 6.25

156.25, 195.3125, 250, 312.5, 390.625, 500, 625

The pll_ref_clk input clock frequency must match the value you specify for the Transceiver reference clock frequency parameter.

tx_serial_clk

Input

NUM_LANES–

Clocks for the individual transceiver channels in 100G Interlaken IP core variations that target an Intel® Arria® 10 device.

clk_tx_common

Output

1

PCS common lane clock driven by the SERDES transmit PLL. The clock rate is the lane rate divided by 40 bits. The clk_tx_common frequency is 156.25 MHz for 6.25 Gbps, 257.8 MHz for 10.3125 Gbps, and 312.5 MHz for 12.5 Gbps per lane.

clk_rx_common

Output

1

Master recovered lane clock. The Interlaken specification requires all incoming lanes to run at the same frequency.

tx_usr_clk

Input

1

Transmit side user data interface clock. To achieve 100 Gbps Ethernet traffic throughput, you must run this clock at one of the following minimum frequencies:

  • 225 MHz in dual segment mode, 12-lane variations
  • 300 MHz in single segment mode and in 24-lane variations

rx_usr_clk

Input

1

Receive side user data interface clock. To achieve 100 Gbps Ethernet traffic throughput, you must run this clock at one of the following minimum frequencies:

  • 225 MHz in dual segment mode, 12-lane variations
  • 300 MHz in single segment mode and in 24-lane variations
mm_clk

Input

1

Management clock. Clocks the register accesses. It is also used for clock rate monitoring and some analog calibration procedures. You must run this clock at a frequency in the range of 100 MHz–125 MHz.

reconfig_clk

Input

1 Clocks the Intel® Arria® 10 transceiver reconfiguration interface. This clock is available only in IP core variations that target an Intel® Arria® 10 device. You should run this clock at a frequency of 100 MHz.
Note: If you change the port name or period of a clock, then you must modify .sdc file to match the corresponding changes.