Visible to Intel only — GUID: nik1411004511308
Ixiasoft
1. About This IP Core
2. Getting Started With the 100G Interlaken IP Core
3. 100G Interlaken IP Core Parameter Settings
4. Functional Description
5. 100G Interlaken IP core Signals
6. 100G Interlaken IP Core Register Map
7. 100G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 100G Interlaken IP core
10. 100G Interlaken IP core User Guide Archives
11. Document Revision History for 100G Interlaken User Guide
A. Performance and Fmax Requirements for 100G Ethernet Traffic
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Specifying the 100G Interlaken IP Core Parameters and Options
2.3. Files Generated for Arria V GZ and Stratix V Variations
2.4. Files Generated for Intel® Arria® 10 Variations
2.5. Simulating the 100G Interlaken IP Core
2.6. Integrating Your IP Core in Your Design
2.7. Compiling the Full Design and Programming the FPGA
2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
3.1. Number of Lanes
3.2. Meta Frame Length in Words
3.3. Data Rate
3.4. Transceiver Reference Clock Frequency
3.5. Include Advanced Error Reporting and Handling
3.6. Enable M20K ECC Support
3.7. Include Diagnostic Features
3.8. Enable Native PHY Debug Master Endpoint (NPDME)
3.9. Include In-Band Flow Control Block
3.10. Number of Calendar Pages
3.11. TX Scrambler Seed
3.12. Transfer Mode Selection
3.13. Data Format
5.1. 100G Interlaken IP Core Clock Interface Signals
5.2. 100G Interlaken IP Core Reset Interface Signals
5.3. 100G Interlaken IP Core User Data Transfer Interface Signals
5.4. 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals
5.5. 100G Interlaken IP Core Management Interface
5.6. Device Dependent Signals
Visible to Intel only — GUID: nik1411004511308
Ixiasoft
4.7.1.2. 100G Interlaken IP Core Packet Mode Operation Example
Figure 13. Packet Transfer on Transmit Interface in Packet Mode
This example illustrates the expected behavior of the 100G Interlaken IP core application interface transmit signals during a packet transfer in single segment packet mode.
The figure illustrates a packet mode data transfer of 179 bytes on the transmit interface into the IP core. In this mode, the 100G Interlaken IP core ignores the itx_sob and itx_eob input signals.
To start a transfer, you assert itx_sop[1] when you have data ready on itx_din_words. At the following rising edge of the clock, the IP core detects that itx_sop[1] is asserted, indicating that the value on itx_din_words in the current cycle is the start of an incoming data packet. When you assert itx_sop[1] , you must also assert the correct value on itx_chan to tell the IP core the data channel source of the data. In this example, the value 2 on itx_chan tells the IP core that the data originates from channel number 2.
During the SOP cycle (labeled with data value d1) and the cycle that follows the SOP cycle (labeled with data value d2), you must hold the value of itx_num_valid[7:4] at 4'b1000 . In the following clock cycle, labeled with data value d3, you must hold the following values on critical input signals to the IP core:
- itx_num_valid[7:4] at the value of 4'b0111 to indicate the current data symbol contains seven 64-bit words of valid data.
- itx_eopbits[3] high to indicate the current cycle is an EOP cycle.
- itx_eopbits[2:0] at the value of 3'b011 to indicate that only three bytes of the final valid data word are valid data bytes.
This signal behavior correctly transfers a data packet with the total packet length of 179 bytes to the IP core, as follows:
- In the SOP cycle, the IP core receives 64 bytes of valid data (d1).
- In the following clock cycle, the IP core receives another 64 bytes of valid data (d2).
- In the third clock cycle, the EOP cycle, the IP core receives six full words (6 x 8 = 48 bytes) and three bytes of valid data, for a total of 51 valid bytes.
The total packet length is 64 + 64 + 51 = 179 bytes.