100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 9/20/2022

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Document Table of Contents 100G Interlaken IP Core Packet Mode Operation Example

Figure 13. Packet Transfer on Transmit Interface in Packet Mode

This example illustrates the expected behavior of the 100G Interlaken IP core application interface transmit signals during a packet transfer in single segment packet mode.

The figure illustrates a packet mode data transfer of 179 bytes on the transmit interface into the IP core. In this mode, the 100G Interlaken IP core ignores the itx_sob and itx_eob input signals.

To start a transfer, you assert itx_sop[1] when you have data ready on itx_din_words. At the following rising edge of the clock, the IP core detects that itx_sop[1] is asserted, indicating that the value on itx_din_words in the current cycle is the start of an incoming data packet. When you assert itx_sop[1] , you must also assert the correct value on itx_chan to tell the IP core the data channel source of the data. In this example, the value 2 on itx_chan tells the IP core that the data originates from channel number 2.

During the SOP cycle (labeled with data value d1) and the cycle that follows the SOP cycle (labeled with data value d2), you must hold the value of itx_num_valid[7:4] at 4'b1000 . In the following clock cycle, labeled with data value d3, you must hold the following values on critical input signals to the IP core:

  • itx_num_valid[7:4] at the value of 4'b0111 to indicate the current data symbol contains seven 64-bit words of valid data.
  • itx_eopbits[3] high to indicate the current cycle is an EOP cycle.
  • itx_eopbits[2:0] at the value of 3'b011 to indicate that only three bytes of the final valid data word are valid data bytes.

This signal behavior correctly transfers a data packet with the total packet length of 179 bytes to the IP core, as follows:

  • In the SOP cycle, the IP core receives 64 bytes of valid data (d1).
  • In the following clock cycle, the IP core receives another 64 bytes of valid data (d2).
  • In the third clock cycle, the EOP cycle, the IP core receives six full words (6 x 8 = 48 bytes) and three bytes of valid data, for a total of 51 valid bytes.

The total packet length is 64 + 64 + 51 = 179 bytes.