100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 9/20/2022

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4.3.2. IP Core Reset

The 100G Interlaken IP core variations have a single asynchronous reset, the reset_n signal. The 100G Interlaken IP core manages the initialization sequence internally. After you de-assert reset_n (raise it after asserting it low), the IP core automatically goes through the entire reset sequence.

Note: Intel® recommends that you hold the reset_n signal low for at least the duration of two mm_clk cycles, to ensure the reset sequence proceeds correctly.
Figure 9.  100G Interlaken IP Core Transceiver Initialization Sequence

The internal initialization sequence implemented by the reset controller included in the 100G Interlaken IP core. In Intel® Arria® 10 devices, the pll_locked signal originates in the external PLL. In other devices, it originates in the 100G Interlaken IP core itself.

Following completion of the reset sequence internally, the 100G Interlaken IP core begins link initialization. If your 100G Interlaken IP core and its Interlaken link partner initialize the link successfully, you can observe the assertion of the lane and link status signals according to the Interlaken specification. For example, you can monitor the tx_lanes_aligned, sync_locked, word_locked, and rx_lanes_aligned output status signals.

In Arria V GZ and Stratix V devices, after you de-assert the reset_n signal, you must wait a certain number of mm_clk cycles before you can successfully access the 100G Interlaken IP core registers using the IP core management interface.

  • In hardware, you must wait 220 mm_clk cycles.
  • In simulation, you must wait 26 mm_clk cycles.

In Intel® Arria® 10 devices, the required wait time from de-asserting the reset_n signal to safely accessing the IP core registers is a function of the internal reset controller. The IP core instantiates an Intel® Transceiver PHY Reset Controller in Intel® Arria® 10 variations.