100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 9/20/2022
Public

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5.6.2. Intel® Arria® 10 External PLL Interface Signals

100G Interlaken IP core variations that target an Intel® Arria® 10 device require an external transceiver PLL to function correctly in hardware. 100G Interlaken IP core variations that target an Arria V or Stratix V device include the transceiver PLLs and do not require that you configure any additional PLLs.

Table 22.   100G Interlaken IP Core Intel® Arria® 10 External PLL Interface Signals

Signal Name

Direction

Width (Bits)

Description

tx_serial_clk

Input

NUM_LANES

High-speed clock for Intel® Arria® 10 transceiver channel, provided from external TX PLL.

tx_pll_locked

Input

1

PLL-locked indication from external TX PLL.

tx_pll_powerdown

Output

1

Output signal from the IP core internal reset controller. The IP core asserts this signal to tell the external PLLs to power down.

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