100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 9/20/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.6.3. Adding the Reconfiguration Controller

100G Interlaken IP core variations that target an Arria V or a Stratix V device require an external reconfiguration controller to function correctly in hardware. 100G Interlaken IP core variations that target an Intel® Arria® 10 device include a reconfiguration controller block and do not require an external reconfiguration controller.

Keeping the Reconfiguration Controller external to the IP core in Arria V and Stratix V devices provides the flexibility to share the Reconfiguration Controller among multiple IP cores and to accommodate FPGA transceiver layouts based on the usage model of your application. In Intel® Arria® 10 devices, you can configure individual transceiver channels flexibly through an Avalon-MM Intel® Arria® 10 transceiver reconfiguration interface.

The following simple instructions show you how to instantiate an Intel® Transceiver Reconfiguration Controller and how to connect the design blocks: