100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 9/20/2022

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2.4. Files Generated for Intel® Arria® 10 Variations

The Quartus® Prime software generates multiple files during generation of your 100G Interlaken IP core Intel® Arria® 10 variation.

Figure 5. IP Core Generated Files

In the Quartus Prime software v15.1 release, generating a 100G Interlaken IP core that targets an Intel® Arria® 10 device does not generate a demonstration testbench. To generate the Verilog HDL testbench and example design files in this release, you must click the Generate Example Design button in the 100G Interlaken parameter editor. When you do so, you are prompted to specify the location of the Verilog HDL demonstration testbench and example design files.