100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 9/20/2022

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Document Table of Contents 100G Interlaken IP Core Back-Pressured Packet Transfer Example

Figure 14. Packet Transfer on Transmit Interface with Back Pressure

This example illustrates the expected behavior of the 100G Interlaken application interface transmit signals during a packet transfer with back pressure.

In this example, the 100G Interlaken IP Core accepts the first four data symbols (256 bytes) of a data packet. The clock cycles in which the application transfers the data values d2 and d3 to the 100G Interlaken IP Core are grace-period cycles following the 100G Interlaken IP Core's de-assertion of itx_ready.

The 100G Interlaken IP Core supports up to 4 cycles of grace period, enabling you to register the input data and control signals, as well as the itx_ready signal, without changing functionality. The grace period supports your design in achieving timing closure more easily. In any case you must ensure that you hold itx_num_valid at the value of 0 when you are not driving data.

You can think of this interface as a FIFO write interface. When itx_num_valid[7:4] is nonzero, both data and control information (including itx_num_valid[7:4] itself) are written to the transmit side data interface. The itx_ready signal is the inverse of a hypothetical FIFO-almost-full flag. When itx_ready is high, the 100G Interlaken IP Core is ready to accept data. When itx_ready is low, you can continue to send data for another 6 to 8 clock cycles of tx_usr_clk.