100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 9/20/2022

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7.5. CRC24 Error Injection

The 100G Interlaken IP core supports the injection of CRC24 errors on the Interlaken link for validation of the Interlaken link partner's error handling, and for validation of this IP core's error handling in a loopback configuration.

This feature is available if you turn on Include diagnostic features in the 100G Interlaken parameter editor.

To force the IP core to inject a bit error in the output to the Interlaken link, you write the value of 1 to bit [0] of the 100G Interlaken IP core ERR_INJECT register at offset 0x102. This change to the register field value forces the IP core to inject a single bit error, which cause one or possibly more CRC24 errors.

Before you can inject a second bit error, you must write the value of 0 to the register. Intel® recommends that you write the value of 1 and then the value of 0 to inject a single bit error, rather than waiting until you want to inject a second error before writing the value of 0 to clear the register.

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