100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 9/20/2022

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Document Table of Contents

4.1.4. Management Interface

The management interface provides access to the 100G Interlaken IP core internal status and control registers. This interface does not provide access to the hard PCS registers on the device.

The management interface complies with the Avalon Memory-Mapped (Avalon-MM) specification defined in the Avalon Interface Specifications.